The present invention relates to signal generators and more specifically to a generator for producing clock signals used to time the logic operations within a computer. Typically such generators consist of a crystal oscillator and counter for producing clock signals of different periods depending on the count information.
The present invention, however, teaches a variable frequency delay line clock having a number of different clock frequencies which can be machine selected on a cycle to cycle basis depending on the specific operation being performed. With such a clock signal generator, the period of each clock cycle can be varied to enable the effects of a clock signal transition to ripple through the computer before the next clock period. Examples of operations requiring differing clock periods are an ADD, which requires additional time due to the carry delays, as opposed to an EXCLUSIVE OR, which does not. The present clock signal generator therefore allows the computer to adjust the timing of its operations to minimize its computational time and not be dependent on the worst case time path of any one operation.